Reconstructed wafers, including high density electronic devices, are typically formed by fabricating a silicon wafer with embedded electronic modules (e.g., chip scale components) using a molding process. Most embedded chip scale components, referred to as electronic modules, include various circuitry contained within a housing and electrical contacts along one surface or another of the housing. During the molding processes, the desired chip scale components are typically oriented on a mounting surface with the electrical contacts facing upward or downward relative to the mounting surface. That is, the electrical contacts along the surface of the housing are located on a housing surface proximate the mounting surface or on a housing surface opposite thereof. As the housings may be stacked, electronic contacts and vias must be provided in order to electrically connect the housing during fabrication steps. Particular care is taken so that the reconstructed wafers can utilize traditional semiconductor manufacturing equipment, processes and technology for such fabrication.
Integrated-ultra high density (iUHD) circuits often contain sub-modules stacked on other sub-modules. The iUHD circuits and sub-modules are formed by sequential deposition and patterning of dielectric and metal layers in a reconstructed wafer process. Multi-layer buried vias are used to create interconnections. Lamination based PCB technology also allows for multi-layer buried vias. Such multi-layered buried vias may be entirely contained (i.e., not exposed externally at either surface).
For example, a portion of a typical laminated printed circuit board 900 is shown in FIGS. 9A-E in various stages of fabrication. In FIGS. 9A-E, multi-layered vias 902 is used to create interconnections between layers 904, 906, 908 and circuitry (not shown). The vias 902 are commonly fabricated in build-up circuits by forming the vias 902 at each layer 904, 906, 908. Upon formation, each via 902, effectively a hole, must be filled and planarised as each of layer 904, 906, and 908 is formed. As can be seen, the filled and planarised holes are stacked to create the vias 902. This technology is typically only useful at geometries above 19 μm.
Creating such filled vias requires extra processing and capabilities that are difficult and not universally available. Additionally, the filling and planarising of the filled vias poses a significant fabrication challenge. Still further, the vias need to be stacked, which increases fabrication complexity on each layer.
Referring now to FIGS. 10A-E, a portion of a typical reconstructed wafer 1000 is shown in FIGS. 10A-E in various stages of fabrication. As the reconstructed wafer 1000 may utilize semiconductor fabrication systems and methods, smaller geometries, say down to 5 μm, may be accomplished. However, a metal pad 1003 must be place on layer 1002. Via 1005 can be filled as the second layer 1006 is formed. As best seen in FIG. 10D, a second via 1007 can be formed and filled when the next layer 1008 is formed (see FIG. 10E). As can be seen, the vias 1005, 1007 inefficiently zig-zag upwards (the zig-zag or extra area is also commonly referred to as a job or dog-bone).
For iUHD applications particularly, these filled vias that dog-bone across intermediate layers undesirably consume real estate. The necessary punctured planes and complicated routing are also undesirable. Further, the lengthened connection pathways increase the resistance of the connection.